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hdlcoder std_logic_vector to stateflow type

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borzack
borzack on 14 Oct 2020
Answered: Kiran Kintali on 22 Dec 2020
Hi
I've a following vhdl code
signal a : std_logic_vector(10 downto 0);
signal b : std_logic_vector(10 downto 0);
a<=b;
My goal is to rewrite in stateflow and reproduce it by hdlcoder.
is there an easy way to do it?
Thanks

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Answers (2)

Aman Vyas
Aman Vyas on 22 Dec 2020
Hi,
You can use Stateflow HDL Code generation workflow where you can try to restructure your logic in the form of Finite State Machines (FSM), notation diagram or state transition diagram.
You can use a chart to model a finite state machine or a complex control algorithm intended for realization as an ASIC or FPGA. When the model meets design requirements, you then generate HDL code (VHDL® or Verilog®) that implements the design embodied in the model. You can simulate and synthesize generated HDL code using industry standard tools, and then map your system designs into FPGAs and ASICs.
For more info you can refer the following link :
Hope it helps !

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Kiran Kintali
Kiran Kintali on 22 Dec 2020
Attached simple Stateflow chart will generate the code you are looking for.

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