Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.

2 vues (au cours des 30 derniers jours)
Eduardo Flores
Eduardo Flores le 27 Déc 2020
Réponse apportée : YP le 21 Nov 2022
After compiling an FPGA in the loop simulink model with VHDL Verifier for Xilinx or Altera devices the new model with the FIL object appears. On windows, a new terminal shows that a new bitstream is being generated but on Ubuntu 18.05, no file is ever created. Am i missing a configuration step?
  1 commentaire
Cau Tran
Cau Tran le 11 Août 2022
I also had this problem. Can anyone give me advice for this one?
FIL does not generate the bitstream file.

Connectez-vous pour commenter.

Connectez-vous pour répondre à cette question.

Réponses (1)

YP
YP le 21 Nov 2022
Can you check if xterm is installed?
FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html

Catégories

En savoir plus sur FPGA, ASIC, and SoC Development dans Help Center et File Exchange

Tags

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by