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Last seen: 29 jours il y a |  Actif depuis 2021

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Results in FPGA-in-loop is different from Vivado simulation and how to debug
Did you set Reset asserted level to 'Active-low'?

5 mois il y a | 0

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Failed to download the third-party software: FTDI JTAG D2XX library
Please refer to this solution. https://www.mathworks.com/matlabcentral/answers/2017321-the-404-error-when-installing-hdl-verifi...

10 mois il y a | 0

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AXI manager not working with Vivado 2023.1
Hi Dan, Vivado 2023.1 will be supported in R2024a. It's not recommended to use this version for R2023a because it hasn't been t...

12 mois il y a | 0

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Issue Connecting to Xilinx FPGA Board for Simulation （Windows ，ZYNQ） Error:Did not receive version information from the hardware.
As mentioned on this help doc. https://www.mathworks.com/help/hdlverifier/ug/fpga-board-editor-reference.html If you are usin...

environ un an il y a | 0

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HDL Coder FPGA In The Loop, Error: There is no current hw_target
The message means it failed to program FPGA with JTAG, which should not happen if you are using Ethernet interface. Please be m...

plus d'un an il y a | 0

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Issue Connecting to Xilinx FPGA Board for Simulation
I am unable to find the manual for this board online. I can double check your pin setting if you can direct me to any doc/manual...

plus d'un an il y a | 0

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Issue Connecting to Xilinx FPGA Board for Simulation
Have you installed adept2? https://www.mathworks.com/help/supportpkg/xilinxfpgaboards/ug/InstallDigilentAdept2Runtime.html

plus d'un an il y a | 0

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Is it possible to do co-cimulation for target Nexys A7?
We don't support Neyxs A7 board out-of-the-box, but you can create a custom board for FPGA-in-the-loop simulation. I think JTAG...

plus d'un an il y a | 0

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Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.
Can you check if xterm is installed? FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html

plus d'un an il y a | 0

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Set up HDL verifier
The command line window shows "Expected programming file not generated". You may need to check the project log see why the bit ...

plus d'un an il y a | 0

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Bitstream generation problem in HDL coder
At the last step in HDL Workflow Advisor, the FIL project will be synthesized, and then an external shell will pop up to continu...

environ 2 ans il y a | 0

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HDL Verifier Max Bit Width Using System Object
Hi David, Do you mean FIL system object? FIL doesn't support sytem verilog HDL. Can you attach your code and elaborate your wor...

plus de 2 ans il y a | 0

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Xilinx ZCU111 OFDM example doesn't load
Can you rerun the hardware setup for the support package? Please follow "Hardware Setup" section as mentioned in https://www.m...

environ 3 ans il y a | 1

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Error in example "5G NR Cell Search Using Xilinx RFSoC Device"
Hi, Do you mean you have successfully finished the last 'load' screen of socBuilder, but saw error when you click the 'Monitor ...

plus de 3 ans il y a | 0