periodic sample time error
28 vues (au cours des 30 derniers jours)
Afficher commentaires plus anciens
i am simulating speed control of BLDC using FPGA .i have completed the model but i m getting one error "The periodic sample time 1000000.0 is not allowed because the ratio of this sample time over base rate (1.0E-6) is greater than the maximum value of uint32." plz help me
2 commentaires
Yao Li
le 14 Mai 2013
I think for the BLDC, the unit of the frequence of the input signal is kHz, thus, what you really need is a much smaller sample time. However, simulink can not generate this kind of signal or the simulation speed is too slow with a kHz frequency. Try to carry out HIL tests or use a reasonable frequency to verify your DC model first.
Réponses (0)
Voir également
Catégories
En savoir plus sur FPGA, ASIC, and SoC Development dans Help Center et File Exchange
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!