Simulation of matlab generated vhdl code leads to Errors

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Anselm
Anselm le 22 Juil 2013
I want to implement an dsp algorithm on an fpga with the matlab hdlcoder. The m-functions work both fine. (floating and fixed point) The hdlcoder workflow finishes without errors or warnings. (I use the workflow up to the stage, when the vhdl code is generated.) But when i simulate the generated vhdl in Xilinx ISim it does not work. I tried simulating in ModelSim, too. The Errors were the same. (There´s always some not defined signal value "...metavalue..." "...returning false")
I use indexed persistent vectors, because there´s a lot "single instruction - multiple data" in the algorithm. This vectors lead to registers not RAM, because of parallel reading and writing. But this is wanted. I think some thing about the indexed vectors leads to the Errors. When i strip down the algorithm, at some point when only some counters are left, it starts to work in ISim.
I read all restrictions about variables in M-Code for vhdl generation. I think i not missing something. And the hdlcoder trows no errors.
Could it be something about the conversion from one-based indexes in Matlab to zero-based in vhdl?
I noticed another odd thing: The simulation starts with all zeros as init values in spite of the "persistent variable; if isempty() ... variable= x..." statements in the mcode.
My suspicion is that some variable i use for indexing has no initial value and this causes the Simulator to stop. But this just guessing.

Réponses (1)

Kiran Kintali
Kiran Kintali le 24 Mai 2021
HDL Coder handles MATLAB one based indexing and converts the logic to zero based indexing when generating VHDL / Verilog code.
simple design that shows MATLAB one based-index
function y = dut(u, i)
y = u(i); % access here is one-based
end
testbench that shows one based variables
u_vec = uint8(1:10);
for ii=int32(1:10)
y(ii) = dut(u_vec, ii); % one based index variable 'ii'
end
u_vec
y
compile the design code (dut.m) using HDL Coder
>> codegen -config:hdl -args {uint8(1:10), int32(0)} dut
### Begin VHDL Code Generation
### Generating HDL Conformance Report dut_hdl_conformance_report.html.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Working on dut as dut.vhd.
### Generating package file dut_pkg.vhd.
### Generating Resource Utilization Report resource_report.html.
Code generation successful.
open the generated dut.vhd file
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.dut_pkg.ALL;
ENTITY dut IS
PORT( u : IN vector_of_std_logic_vector8(0 TO 9); -- uint8 [10]
i : IN std_logic_vector(31 DOWNTO 0); -- int32
y : OUT std_logic_vector(7 DOWNTO 0) -- uint8
);
END dut;
ARCHITECTURE rtl OF dut IS
-- Signals
SIGNAL u_unsigned : vector_of_unsigned8(0 TO 9); -- uint8 [10]
SIGNAL i_signed : signed(31 DOWNTO 0); -- int32
SIGNAL y_tmp : unsigned(7 DOWNTO 0); -- uint8
BEGIN
outputgen: FOR k IN 0 TO 9 GENERATE
u_unsigned(k) <= unsigned(u(k));
END GENERATE;
i_signed <= signed(i);
--HDL code generation from MATLAB function: dut
y_tmp <= u_unsigned(to_integer(i_signed - 1)); --%%%% observe zero based access here
y <= std_logic_vector(y_tmp);
END rtl;

Produits

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