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Configuration in FPGA (RFSoC) while implementing WLAN HDL transmitter and receiver modules
Consider that clocks and sample rates are two different entities. The PL (Programmable Logic) clocks typically operate in the MH...
5 mois il y a | 0
| A accepté
Configuration in FPGA (RFSoC) while implementing WLAN HDL transmitter and receiver modules
Hi Yun, Firstly, the SoC example you referred to doesn't include the transmitter model that we shipped in the recent R24b re...
6 mois il y a | 0
How to modify the input ports of the CCSDS LDPC decoder and reduce its BRAM resource consumption
Hi, In CCSDS LDPC decoder, you can configure the input port width by simply change the data type of the "decSampleIn" in the...
6 mois il y a | 0
| A accepté
Change configurations of the WLAN HDL examples of transmitter and receiver
Hi Yun-Tsun, Yes, the two examples are compliant with 802.11 a/n/ac and supports OFDM based tranmitter and receiver. The fo...
7 mois il y a | 0
| A accepté
Uploading and Profiling the HDL OFDM Reference Example on USRP X310
Can you try this workflow Getting Started with NI USRP Targeting Workflow
10 mois il y a | 1
Run UDP as Simulator for OFDM TX/RX
Hi, I was unable to reproduce this issue. I tried in R2024a and was able to get all the outputs and the constellation. I have ...
plus d'un an il y a | 0
OFDM implementation over rayleigh channel with doppler , matlab(simulink) to hdl
You can check this example from the Wireless HDL Toolbox. https://www.mathworks.com/help/wireless-hdl/ug/hdl-implementationof-f...
plus d'un an il y a | 0
I am facing an issue while converting my OFDM code from matlab to HDL during fixed point conversion
Hi Siddhardha, HDL code generation of OFDM modulator and demodulator, you can find below https://in.mathworks.com/help/wireles...
plus d'un an il y a | 0
ccsdsRSEncode , CCSDS RS Encoder input problem
Hi, The ccsdsRSEncode function and CCSDS RS Encoder Simulink block handles the interleaving based on the user's selection of I...
plus d'un an il y a | 0
how to perform frequency shift or frequency correction in simulation using HDL NCO and LOOKUP table(LUT) in order to generate HDL code
Your logic can be replicated with the help of the NCO HDL followed by mulitplier. Similar application, we used to correct the fr...
plus de 2 ans il y a | 0
| A accepté
Is it possible to extend the bus width from 32bit(16 for I,16 for Q) to 64bit(32 for I, 32 for Q) in HDL QAM Transmitter and Receiver?
We dont have an option to do automatically by configuring a parameter. You can start changing the symbol modulator and pulse sha...
environ 3 ans il y a | 0
| A accepté
HDL QPSK Transmitter and Receiver CFO problem
Yes, simply you can provide the Symbol rate in the Inputdata mask, change the Carrier Frequency Offset (in Hz) corresponding to...
plus de 3 ans il y a | 0
HDL QPSK Transmitter and Receiver CFO problem
Hi Ali Shan, I am fine, hope you are doing well. The more average length gives a better/accurate estimate, but that d...
plus de 3 ans il y a | 0
HDL QPSK Transmitter and Receiver CFO problem
Hi Ali Shan, The value 0.125 implied in the algorithm that we choose. Implemented correlation based estimation, as the r...
plus de 3 ans il y a | 0
HDL QPSK Transmitter and Receiver CFO problem
Hi Ali Shan, In QPSK single carrier model, the carrier frequency estimates in steps of coarse and fine estimates which a...
plus de 3 ans il y a | 0
| A accepté
Modifying the QPSK RX for TDD for hw/sw design in ad9361
Hi Muhammad, The Model you are referring is not supported for discrete valid of inputs, and the receiver is expecting alw...
presque 4 ans il y a | 0
HDL optimized QPSK TX and RX combined
Hi, There are some limitations in the model due to receiver architecture. Here, Timing recovery would be self synchronizin...
plus de 4 ans il y a | 0
Addition of signals in simulink
Hi, To demodulate the I and Q signals without using QPSK demodulator block can be done for the hard decision. You can get I...
plus de 4 ans il y a | 0
