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Changing HDL FIR filter numerator while simulation is running

You can set the property Coefficients Source to input port and feed the coefficients via the input port. This will allow you to ...

Changing HDL FIR filter numerator while simulation is running

You can set the property Coefficients Source to input port and feed the coefficients via the input port. This will allow you to ...

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IIR Filter Coefficant Value

Click on File -> Export. There is an option to export the coefficients to the workspace (SOS, G will be exported as variables ac...

IIR Filter Coefficant Value

Click on File -> Export. There is an option to export the coefficients to the workspace (SOS, G will be exported as variables ac...

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Is matlab R2020a compatible with the latest xilinx system generator 2019.1?

I believe the answer is no. The question has been answered in this post.

Is matlab R2020a compatible with the latest xilinx system generator 2019.1?

I believe the answer is no. The question has been answered in this post.

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Hi, I am using R2014b but cant find the HDL code in Code menu, only C/C++ code. what should i do to genarate a HDLcode for my simulink model.

You likely do not have HDL Coder installed. Type ver at the MATLAB command prompt to see if you have HDL Coder installed.

Hi, I am using R2014b but cant find the HDL code in Code menu, only C/C++ code. what should i do to genarate a HDLcode for my simulink model.

You likely do not have HDL Coder installed. Type ver at the MATLAB command prompt to see if you have HDL Coder installed.

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Do Enabled Subsystems use multiplexers in generated HDL code?

In order to get different rates, either through clock enables or through multiple clocks, you need to model the signals at diffe...

Do Enabled Subsystems use multiplexers in generated HDL code?

In order to get different rates, either through clock enables or through multiple clocks, you need to model the signals at diffe...

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'/Serializer1D/HDL1DSe' error occurred when invoking 'getOutputSizeImpl' method of 'hdl.serializer1D'

I was able to avoid the error by setting the dimension of inputA to 1. Model attached.

'/Serializer1D/HDL1DSe' error occurred when invoking 'getOutputSizeImpl' method of 'hdl.serializer1D'

I was able to avoid the error by setting the dimension of inputA to 1. Model attached.

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How can I get the input names of the first level only in my simulink model?

You can use the SearchDepth parameter to specify the depth of the search. sysIns = find_system(bdroot,'SearchDepth',1, 'BlockT...

How can I get the input names of the first level only in my simulink model?

You can use the SearchDepth parameter to specify the depth of the search. sysIns = find_system(bdroot,'SearchDepth',1, 'BlockT...

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Warning: the font "Times" is not available, so "Lucida Bright" has been substituted, but may have unexpected appearance or behavor. Re-enable the "Times" font to remove this

What operation are you trying to eprform? Are you trying to generate HDL Code? If yes, do you have HDL Coder installed and lice...

Warning: the font "Times" is not available, so "Lucida Bright" has been substituted, but may have unexpected appearance or behavor. Re-enable the "Times" font to remove this

What operation are you trying to eprform? Are you trying to generate HDL Code? If yes, do you have HDL Coder installed and lice...

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I am trying to run the Xilinx Demo in simulating but I get "Error in 'sysgenSSRIFFT/I.IM': Initialization commands cannot be evaluated."

"System Generator for DSP" is a third-party blockset provided by Xilinx. For questions related to System Generator, please conta...

I am trying to run the Xilinx Demo in simulating but I get "Error in 'sysgenSSRIFFT/I.IM': Initialization commands cannot be evaluated."

"System Generator for DSP" is a third-party blockset provided by Xilinx. For questions related to System Generator, please conta...

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HDL coder sharing factor and axi-stream valid signal

I will likely need a little more information on exactly which FIR block you are using, but you can put in a sharing factor on th...

HDL coder sharing factor and axi-stream valid signal

I will likely need a little more information on exactly which FIR block you are using, but you can put in a sharing factor on th...

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Is the DSP Builder for Intel FPGAs compatible with the Computer Vision Toolbox?

Did you mean to ask about Vision HDL Toolbox and not Computer Vision Toolbox? In that case, the HDL code you generate from Visio...

Is the DSP Builder for Intel FPGAs compatible with the Computer Vision Toolbox?

Did you mean to ask about Vision HDL Toolbox and not Computer Vision Toolbox? In that case, the HDL code you generate from Visio...

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How to change frequency of sine wave on FPGA IO334?

One way to do this is by using the NCO HDL Optimized block and change the phase increment. Here is an example of how to use the ...

How to change frequency of sine wave on FPGA IO334?

One way to do this is by using the NCO HDL Optimized block and change the phase increment. Here is an example of how to use the ...

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Matlab Implementation on Hardware Devices

Here is an example of how to go from MATLAB code to generating HDL code using Vision HDL Toolbox. You can then use the Vision H...

Matlab Implementation on Hardware Devices

Here is an example of how to go from MATLAB code to generating HDL code using Vision HDL Toolbox. You can then use the Vision H...

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How to switch to visualize the output of FFT HDL Optimized in the frequency domain ?

If you did this in Simulink, you can send the output of the Simulink subsystem to the Spectrum Analyzer and do the analysis ther...

How to switch to visualize the output of FFT HDL Optimized in the frequency domain ?

If you did this in Simulink, you can send the output of the Simulink subsystem to the Spectrum Analyzer and do the analysis ther...

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Why FFT HDL Optimized has not output?

It looks like the input valid is not being set to the right pulse width to feed in all the input data for a given frame. Please ...

Why FFT HDL Optimized has not output?

It looks like the input valid is not being set to the right pulse width to feed in all the input data for a given frame. Please ...

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Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?

I'd first suggest that you run the generated HDL and Testbench to make sure that the HDL design is working correctly. The next ...

Why is the output of the FFT HDL Optimized block zeros in Vivado's Simulation ?

I'd first suggest that you run the generated HDL and Testbench to make sure that the HDL design is working correctly. The next ...

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How to implement a real-time fft for FPGA with matlab or simulink ?

The HDL code from the FFT HDL Optimized does do processing in real-time with streaming samples. It also allows you to process mu...

How to implement a real-time fft for FPGA with matlab or simulink ?

The HDL code from the FFT HDL Optimized does do processing in real-time with streaming samples. It also allows you to process mu...

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MATLAB function block doesn't generate synthesizable HDL.

It appears that you have floating point values in your MATLAB code. If you want to retain floating point numerics for your HDL,...

MATLAB function block doesn't generate synthesizable HDL.

It appears that you have floating point values in your MATLAB code. If you want to retain floating point numerics for your HDL,...

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Synthesizable VHDL code for filter design (using FDATOOL) not obtained for MATLAB R2015a

This is becasuse the filter is not quantized. Use the Quantization panel in fdatool to create a fixed-point biquad filter. If y...

Synthesizable VHDL code for filter design (using FDATOOL) not obtained for MATLAB R2015a

This is becasuse the filter is not quantized. Use the Quantization panel in fdatool to create a fixed-point biquad filter. If y...

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how to report time-scale of simulink model

If you set the sample times on the sources such that the HDL Subsystem sees different Simulink rates, that will convey the right...

how to report time-scale of simulink model

If you set the sample times on the sources such that the HDL Subsystem sees different Simulink rates, that will convey the right...

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How do i design a synthesizable FFT with Simulink or Matlab for later on FPGA Implementation ?

The examples in this page should be a good start for you to design the input and generate hdl code.

How do i design a synthesizable FFT with Simulink or Matlab for later on FPGA Implementation ?

The examples in this page should be a good start for you to design the input and generate hdl code.

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How can i watch the content of a HDL RAM Block during simulation

I do not believe this capability exists currently. Could you please get in touch with MATLAB support to register this request so...

How can i watch the content of a HDL RAM Block during simulation

I do not believe this capability exists currently. Could you please get in touch with MATLAB support to register this request so...

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The function block "Integrate and Dump" (Simulink) is not supported for HDL code generation. Is there a similar one which is supported for HDL code generation? Thanks a lot!

There isn't a direct single block substiture for the Integrate and Dump block, but the attached model shows the way you can mode...

The function block "Integrate and Dump" (Simulink) is not supported for HDL code generation. Is there a similar one which is supported for HDL code generation? Thanks a lot!

There isn't a direct single block substiture for the Integrate and Dump block, but the attached model shows the way you can mode...

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QPSK Modulation Verilog Code generation error?

It appears that you need to covert the design to use fixed-point as well as set appropriate sample rates for your sources. Pleas...

QPSK Modulation Verilog Code generation error?

It appears that you need to covert the design to use fixed-point as well as set appropriate sample rates for your sources. Pleas...

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I'm getting this error and I'm unable to figure out this. Please help

Please check if you have an HDL simulator that is supported. Here is the list supported by HDL Verifier: https://www.mathworks.c...

I'm getting this error and I'm unable to figure out this. Please help

Please check if you have an HDL simulator that is supported. Here is the list supported by HDL Verifier: https://www.mathworks.c...

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HDL Coder streaming input instead of vector

In this case, you want to use the Unbuffer block to stream the data in sample by sample.

HDL Coder streaming input instead of vector

In this case, you want to use the Unbuffer block to stream the data in sample by sample.

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How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?

Here is an equivalent Simulink model. Data comes in through the Signal To Workspace blocks whose input can come in from any wor...

How do I call an FFT multiple times with HDL Coder: System Object Methods in Loops?

Here is an equivalent Simulink model. Data comes in through the Signal To Workspace blocks whose input can come in from any wor...

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How to configure modelsim in Matlab?

You can specify the vsimdir property value pair via vsimargs to vsimulink. See this page for details. You should also be able t...

How to configure modelsim in Matlab?

You can specify the vsimdir property value pair via vsimargs to vsimulink. See this page for details. You should also be able t...

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Matlab HDL coder target frequency

The FFT HDL Optimized block & System object allow you to send 2^N samples per clock into the FFT. If you are able to get an FPGA...

Matlab HDL coder target frequency

The FFT HDL Optimized block & System object allow you to send 2^N samples per clock into the FFT. If you are able to get an FPGA...

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Discrete FIR Filter input port

As you have observed, all the coefficients are to be provided at the input interface. One way to do this would be to take each ...

Discrete FIR Filter input port

As you have observed, all the coefficients are to be provided at the input interface. One way to do this would be to take each ...

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