Atan2 block native floating point single HDL generation needs more pipelining

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Hi, I'm using the atan2 block with single precision to generate HDL and with the MAX latency of 42 clocks but it only achieves a clock rate of about 330 MHz (need more like 360 MHz) in my FPGA synthesis run. The critical path seems to be a stage of DSP48's chained together in cascade mode but without pipelining in the cascade. Is there a way to increase the pipelining internal to the atan2 block? Why does this block have no MIN or MAX range (MIN = MAX = 42). I think if you could just add more pipelining it would be able to run much faster. Retiming does not seems to be able to place registers where needed in this case.
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Michael Pratt
Michael Pratt on 10 Aug 2022
Yeah I did end up using the Complex to Magnitude Angle block. But I still think the atan2 block's timing could be improved significantly with a few underlying design changes. I discovered that if some bit slicing between the multiply and pipeline delays was moved to after the pipeline delays, synthesis was able to map the pipeline delays properly to the DSP48. The bit slicing gets in the way of optimal synthesis mapping in FPGAs (though the way it's implemented may be preferable for ASIC targets). I've often found that it's hard to make a design optimal for both ASIC and FPGA designs because often a design maps more efficiently for one than the other.

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Accepted Answer

Bharath Venkataraman
Bharath Venkataraman on 11 Aug 2022
I am glad that using the Complex to Magnitude Angle block worked out for you. Adding that option as an answer in case others run into this issue.
I will pass on your feedback to the relevant team.

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