Tensilica DSP Code Generation Toolbox
Generate C code optimized for Cadence Tensilica DSP processors
Highlights
- Enable the rapid porting of MATLAB and Simulink models to Tensilica DSPs
- Perform functional verification and cycle-accurate execution of generated code using processor-in-the-loop (PIL) simulation
- Code replacement libraries (CRL) ensure that generated code is optimized for the Tensilica architecture
- Code execution profiling to evaluate execution time of algorithms on the specified processors
- Integration with Cadence SDK toolchain (compiler, assembler, linker, archiver)
Description
Differentiated hardware tailored to the application requirements is essential to achieve optimal performance and energy efficiency. Customers can quickly create differentiated, domain-specific processors for their application needs with the help of Cadence® Tensilica® IP’s proven technology, including Tensilica Xtensa® extensible processors, a broad range of high-performance application-specific DSPs, a comprehensive development toolchain, and unparalleled support.
MATLAB® and Simulink® are widely used for modeling and simulating real-time dynamical systems. To verify the performance of MATLAB and Simulink models on Cadence Tensilica DSPs, the models must first be converted to C code using code generation tools from MathWorks®. This generated code can be integrated into existing projects and must be compiled, downloaded, and executed on a processor or the processor’s Instruction Set Simulator (ISS).
The functional verification of the execution (checking the similarity of the outputs between MATLAB and Simulink and the processor/ISS) can be performed. The cycle performance measurement (the number of cycles taken to run the code on the processor/ISS) can also be done.
The Tensilica DSP Code Generation Toolbox enables the rapid porting of MATLAB and Simulink models on Tensilica DSPs. End users can start designing signal processing algorithms in DSP System Toolbox™ and generate code to deploy onto Tensilica DSPs before silicon exists or while configuring their DSPs to optimize the system design. The Hardware Support Package (HSP) enables users to generate, optimize, build, execute, and verify code from MATLAB and Simulink on Tensilica DSPs.
The HSP provides the following features that let users:
- Generate C/C+ code from MATLAB and Simulink models/scripts and deploy on an ISS
- Replace standard Simulink blocks with Cadence IP blocks using CRL
- Specify compiler, linker, assembler, and archiver toolchains, and target the processor’s ISS
- Communicate over a TCP/IP channel between MATLAB and Simulink and target the processor's ISS
- Processor-in-the-loop:
- Compare MATLAB and Simulink simulation results with the results on the Tensilica ISS
- Evaluate the run time of algorithms on the specified processor
The HSP supports select Tensilica DSPs within the ConnX, MathX, HiFi, and Vision DSP families. For more information, refer to the related Cadence white paper.
To download the HSP for using with MATLAB and Simulink, please see the repository in MATLAB File Exchange.
Cadence Design Systems, Inc
2655 Seely Avenue
San Jose, CA 95134
UNITED STATES
Tel: 408-943-1234
info@cadence.com
www.cadence.com
Required Products
Recommended Products
Platforms
- Linux
- Macintosh
Support
- Consulting
- Training
Product Type
- Embedded Hardware - MCU, DSP, FPGA
- Embedded Software - Tools, IDE, RTOS
Tasks
- Acoustics
- Digital Signal Processing
- Embedded Systems
- Image Processing and Computer Vision
Industries
- Automotive
- Communication Devices
- Computer Electronics
- Consumer Electronics
- Semiconductor