Main Content

Data Converters

Simulate successive-approximation-register (SAR) and flash analog to digital data converters (ADC)

Simulate and analyze performance metrics of analog to digital data converters. Start from complete system-level models of typical ADC architectures, such as SAR or flash ADC. Modify ADC parameters until you reach your desired system specifications. Use Measurements and Testbenches to validate your design.


expand all

Sampling Clock SourceGenerate clock signal with aperture jitter (Since R2019a)
Delta Sigma ModulatorModel a discrete delta sigma modulator based ADC (Since R2021b)
Flash ADCN-bit ADC with flash architecture (Since R2019a)
SAR ADCN-bit successive approximation register (SAR) based ADC (Since R2019a)
Interleaved ADCTime-interleaved ADC model (Since R2023b)
Binary Weighted DACN-bit DAC based on R-2R weighted resistor architecture (Since R2020a)
Segmented DACConvert large digital input to analog signal using arrangement of smaller DACs (Since R2021a)