Data Converters

Simulate successive-approximation-register (SAR) and flash analog to digital data converters (ADC)

Simulate and analyze performance metrics of analog to digital data converters. Start from complete system-level models of typical ADC architectures, such as SAR or flash ADC. Modify ADC parameters until you reach your desired system specifications. Use Measurements and Testbenches to validate your design.

Blocks

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Building Blocks

Sampling Clock Source	Generate clock signal with aperture jitter
Delta Sigma Modulator	Model a discrete delta sigma modulator based ADC

ADC Reference Architectures

Flash ADC	N-bit ADC with flash architecture
SAR ADC	N-bit successive approximation register (SAR) based ADC

DAC Reference Architectures

Binary Weighted DAC	N-bit DAC based on R-2R weighted resistor architecture
Segmented DAC	Convert large digital input to analog signal using arrangement of smaller DACs

Topics

Compare SAR ADC to Ideal ADC
This example shows a comparison of the SAR ADC from the Mixed-Signal Blockset™ to the ideal ADC model with impairments presented in Analyzing Simple ADC with Impairments.
Design and Evaluate Interleaved ADC Using System Object
This example shows how to use System Objects to model and evaluate the performance of an interleaved ADC.
Effect of Metastability Impairment in Flash ADC
This example shows how to customize a flash Analog to Digital Converter (ADC) by adding the metastability probability as an impairment.
Compare Binary Weighted DAC to Ideal DAC
This example shows a comparison of the Binary Weighted DAC from the Mixed-Signal Blockset™ to an ideal DAC model.
Delta Sigma Modulator Data Converter with Half-Band Filter for Decimation
Use the delta sigma modulator data converter for an analog-to-digital converter application.

Featured Examples

Analyzing Simple ADC with Impairments

Implement a basic ADC using a Zero-Order Hold block as a sampler. This simple ADC highlights some of the typical impairments introduced in an analog-to-digital converters such as aperture jitter, nonlinearity, quantization, and saturation. This example shows how to measure the effects of such impairments using a Spectrum Analyzer block and the ADC AC Measurement block from the Mixed-Signal Blockset™. To better approximate real-world performance, you can individually enable the impairments in the model.

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Design and Evaluate Successive Approximation ADC Using Stateflow

Design and evaluate a 12-bit successive approximation register ADC.

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Subranging ADC

Model a 6-bit Subranging ADC with pipelining and an error correcting second stage.

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Design and Evaluate Interleaved ADC

This interleaved ADC model highlights some of the typical impairments introduced by data converters and their effects on a larger system.

Open Model

Design and Evaluate SAR ADC

Design a SAR ADC using reference architecture and validate the ADC using ADC Testbench.

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Oversampling Interpolating DAC

Model a 12-bit Oversampling Interpolating DAC.

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Design and Evaluate Segmented DAC

Design and evaluate a segmented DAC using reference architecture and validate the DAC using the DAC Testbench. For this example, use the datasheet of AD9775. This is a commercial, off-the-shelf 14-bit DAC from Analog Devices.

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