Memory not Initialized in Simulink HDL causing problems in FPGA simulation.

The FPGA simulation, like modelsim, does not like reading from not initialized memory, it creates undefined signals. But I cannot reproduce this problem in Simulink HDL since all memory are initialized to zero at startup by default.

Is there a way for Simulink to assume that memory at startup is undefined and at least give a warning if it reads from undefined memory?

Answer 1

[Kiran Kintali]

https://www.mathworks.com/help/hdlcoder/ug/rtl-customizations-for-rams.html

RTL Customization Parameters for RAMs

This page describes parameters that reside in the HDL Code Generation > Global Settings > Coding Style tab of the Configuration Parameters dialog box.Initialize all RAM blocks

Enable or suppress generation of initial signal value for RAM blocks. If you specify a nonzero initial value for the RAM, this setting is ignored.

Default: On For RAM blocks, generate initial values of '0' for both the RAM signal and the output temporary signal.

Off: For RAM blocks, do not generate initial values for either the RAM signal or the output temporary signal.

[Jean-Serge Cardinal]

I tried this but I still read zeros at the output of non-initalized memory. I would like Simulink to show an "undefined" state when reading from non-initialized memory. But I guess "undefined" states does not exist in Simulink.

[Kiran Kintali]

I think you are asking for a Simulation behavior change on the RAM blocks. Please reach out to tech support with your request. Thanks