HDL Code: How to feed an FFT a [64x1] vector as an input.

Hello,

I would like to implement an FFT on my FPGA. On my FPGA I receive data continuously with a specific clock one sample after another. I would like to buffer 64 samples and then perform the FFT on those.

The Simulink model that describes the idea (but is not HDL compatible) looks simple:

I created the following example using the HDL optimized FFT and a Buffer outside the Subsystem.

This creates a top level HDL file that uses as an input to the FFT Subsystem an array of std_logic_vectors:

 In1                               :   IN    vector_of_std_logic_vector16(0 TO 63);  -- ufix16_En8 [64]
 ...
 TYPE vector_of_std_logic_vector16 IS ARRAY (NATURAL RANGE <>) OF std_logic_vector(15 DOWNTO 0);

I am know looking for ways to create this buffer that is currently only working in simulink in hardware. Preferably using simple block RAM. Sofar I found the line_buffer (in the eml_hdl_design_patterns library) and the HDL FIFO. But with both I seem to not achieve my goal.

I am happy about any kind of hinds or reference examples. So far my search hasn't revealed anything and I am a little lost how to create a HDL compatible Buffer. Or how else to use the FFT?

[Kiran Kintali]

Can you try attached configuration? If this does not address your issue please reach out to MathWorks support.

 OutputBufferSize inVect = 64;
 FFTLength = 128;

[Fabig]

Thanks for your response. Your example works fine and I don't have an issue with the FFT. I am trying to find a way to implement this buffer in VHDL using the HDL Coder. Sofar I haven't found a way to create an HDL compatible buffer.

[Bharath Venkataraman]

To get all the values at the same time for HDL code generation, you need to use a Tapped Delay block. Set it to 64 delays and it will give you the last 64 values sent in. Since the block does not have an enable, you may need to put it into an enabled subsystem to trigger only on the valid values.

Answer 1

[Bharath Venkataraman]

You do not need to buffer 64 samples and then pass it all at once to the HFL FFT. You can just pass in one sample at a time as you get them. The HDL FFT block will then send out the 64 samples of data after some latency (displayed on mask).

[Fabig]

Sorry that it took me a while. I wanted to test this first and I had some issues comparing the result from the FPGA with the ones generated by simulink. Thanks for the answer.