The issues you were facing are related to mix of incompatible single and double types in the model causing compilation issues in your model. See the updated model with very minor changes.
>> makehdl('EKFforHDLcoder190821/Subsystem')
### Generating HDL for 'EKFforHDLcoder190821/Subsystem'.
### Using the config set for model EKFforHDLcoder190821 for HDL code generation parameters.
### Running HDL checks on the model 'EKFforHDLcoder190821'.
### Begin compilation of the model 'EKFforHDLcoder190821'...
### Applying HDL optimizations on the model 'EKFforHDLcoder190821'...
### Begin model generation.
### Model generation complete.
### Begin VHDL Code Generation for 'EKFforHDLcoder190821'.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_div_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_div_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_add_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_add_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_sub_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_sub_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_mul_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_mul_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_sqrt_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_sqrt_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_atan_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_atan_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_exp_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_exp_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_gain_pow2_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_gain_pow2_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_uminus_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_uminus_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_recip_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_recip_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function/nfp_pow_single as hdl_prj\hdlsrc\EKFforHDLcoder190821\nfp_pow_single.vhd.
### Working on EKFforHDLcoder190821/Subsystem/MATLAB Function as hdl_prj\hdlsrc\EKFforHDLcoder190821\MATLAB_Function.vhd.
### Working on EKFforHDLcoder190821/Subsystem as hdl_prj\hdlsrc\EKFforHDLcoder190821\Subsystem.vhd.
### Generating package file hdl_prj\hdlsrc\EKFforHDLcoder190821\Subsystem_pkg.vhd.
### Code Generation for 'EKFforHDLcoder190821' completed.
### Creating HDL Code Generation Check Report Subsystem_report.html
### HDL check for 'EKFforHDLcoder190821' complete with 0 errors, 1 warnings, and 0 messages.
### HDL code generation complete.
>>
The model genertes HDL code, but you would need to consider further pipelining and fixed-point conversion as necessary to improve generated HDL Code for improving ASIC/FPGA area efficiency and meeting timing/frequency/latency requirements.
Here are some useful links.
Hardware Modeling with MATLAB Code
Specifically look at Model State with Persistent Variables top here
I would highly recommend two day HDL Coder training on best modeling practices for FPGA/ASIC code generation.
Generating HDL Code from Simulink
Day 1 of 2
Preparing Simulink Models for HDL Code Generation
Objective: Prepare a Simulink model for HDL code generation. Generate HDL code and testbench for simple models requiring no optimization.
- Preparing Simulink models for HDL code generation
- Generating HDL code
- Generating a test bench
- Verifying generated HDL code with an HDL simulator
Fixed-Point Precision Control
Objective: Establish correspondence between generated HDL code and specific Simulink blocks in the model. Use Fixed-Point Tool to finalize fixed point architecture of the model.
- Fixed-point scaling and inheritance
- Fixed-Point Designer workflow
- Fixed-Point Tool
- Command-line interface
Generating HDL Code for Multirate Models
Objective: Generate HDL code for multirate designs.
- Preparing a multirate model for generating HDL code
- Generating HDL code with single or multiple clock pins
- Understanding and applying techniques used for clock domain crossing
Day 2 of 2
Optimizing Generated HDL Code
Objective: Use pipelines to meet design timing requirements. Use specific hardware implementations and share resources for area optimization.
- Generating HDL code with the HDL Workflow Advisor
- Meeting timing requirements via pipelining
- Choosing specific hardware implementations for compatible Simulink blocks
- Sharing FPGA/ASIC resources in subsystems
- Verifying that the optimized HDL code is bit-true cycle-accurate
- Mapping Simulink blocks to dedicated hardware resources on FPGA
Using Native Floating Point
Objective: Implement floating point values and operations in your HDL code.
- Why and when to use native floating point
- Target-independent HDL code generation with HDL Coder
- Fixed-point vs. floating point comparison
- Optimization of floating point implementations
Interfacing External HDL Code with Generated HDL
Objective: Incorporate hand-written HDL code and/or vendor party IP in your design.
- Interfacing external HDL code
Verifying HDL Code with Cosimulation
Objective: Verify your HDL code using an HDL simulator in the Simulink model.
- Verifying HDL code generated with HDL Coder
- Comparing manually written HDL code with a "golden model"
- Incorporating HDL code into Simulink for simulation
