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HDL Coder compatibility with Microchip Libero SoC v2024.1 and roadmap for Libero 2025.x support
Which MATLAB releases officially support Libero SoC v2024.1? R2025a, R2025b, and R2026a officially support Libero SoC v2024.1. ...
environ une heure il y a | 0
Will Matlab HDL coder support Altera Agilex 3 and 5 series devices?
Support for Intel/Altera Agilex 3 and Agilex 5 devices is currently part of the future HDL Coder roadmap and is not yet availabl...
8 jours il y a | 0
Using rate transition blocks in HDL coder
A Rate Transition block does not infer a FIFO in HDL, even when ✔ Ensure data integrity during data transfer and ✔ Ensure dete...
13 jours il y a | 0
HDL multi rate simulation
Can you share a sample model? It sounds like you have parts of the design that do not need to be updated at 20e-9s, if that is ...
13 jours il y a | 0
how to deal with stream data to HDLFFT?
Implement FFT Algorithm for FPGA HDL Coder, DSP HDL Toolbox, Simulink This example shows how to implement a hardware-targeted ...
environ un mois il y a | 0
HDL QPSK Transmitter and Receiver example problem
Please reach out to tech support if it is still reproducible. Here is the generated output for the example. >> makehdl('commhdl...
environ un mois il y a | 0
matlab to vhdl conversion
You should consider using MATLAB Copilot to translate your MATLAB to follow Synthesis friendly rules. Here is some guidance to...
environ un mois il y a | 0
Build Linux Image for HDL Coder
Build Custom Linux Image for HDL Coder IP Core https://www.mathworks.com/help/hdlcoder/ug/xilinx-zynq-linux-image-for-custom-bo...
environ un mois il y a | 0
| A accepté
CIC Filter
These two blocks support HDL Code Generation CIC Decimator https://www.mathworks.com/help/dsphdl/ref/cicdecimator.html https:...
environ un mois il y a | 0
I want to generate HDL from a System Object that contains several dsp.FIRFilter objects, the number of which is determined by a Nontunable property
You are correct. HDL Coder (and hardware modeling in general) does not support dynamic behavior in MATLAB code. All structural...
environ 2 mois il y a | 0
| A accepté
HDL Code Generation for Moving Maximum function
HDL Coder does not support Moving Maximum block in DSP System Toolbox out of the box. Consider using the attached model built us...
environ 2 mois il y a | 0
Question
HDL Code Generation for Moving Maximum function
How do I generate HDL Code from Moving Maximum block in DSP System Toolbox?
environ 2 mois il y a | 1 réponse | 0
1
réponseDelay balancing failed when generating HDL code
It looks like you are hitting a delay balancing error due to latency in a feedback look in the model cannot be matched. https...
environ 2 mois il y a | 0
simulink can't map matrie to RAM
Hi, Can you please share the model here or reach out to technical support for additional guidance? Thanks
environ 2 mois il y a | 0
Getting Error while using HDL Coder
If you are still facing the issue please reach out to MathWorks technical support. I tried the example model in R2025b release ...
2 mois il y a | 0
Errors when using HDL coder
Can you reach out to technical support with the reproduction steps? Contact Support - MATLAB & Simulink
2 mois il y a | 0
sampling time mismatch in simulink and harware
You do not have to model at the FPGA clock rate in the Simulink model. There are several strategies possible. HDL Coder Evaluat...
2 mois il y a | 0
An instance of AMD cannot be generated in the HDL Coder
https://www.mathworks.com/help/hdlcoder/ug/generate-hdl-code-amd-floating-point-library.html If you are using a recent release ...
2 mois il y a | 1
| A accepté
How to register a reference design that contains block design, rtl, and xilinx IP core?
HDL Coder has a lot of integration touch points with custom code, custom IP core modules and integrating with Vits Model Compose...
3 mois il y a | 0
generated HDL code failing in cadence AMS
https://www.mathworks.com/help/hdlcoder/index.html HDL Coder generates Synthesizable RTL. For the list of supported...
3 mois il y a | 1
fixdt outof bounds error for data conversion block
This looks like an unexpected behavior and is a bug in the block implementation. https://www.mathworks.com/help/wireless-hdl/u...
3 mois il y a | 0
Import VHDL in simulink
importhdl Import Verilog or VHDL code and generate Simulink model https://www.mathworks.com/help/hdlcoder/ref/importhdl.html ...
3 mois il y a | 0
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share your test model along with the version of MATLAB you are using? We tested with R2025b using the atta...
4 mois il y a | 0
Sine and Cosine HDL Optimised Block
Please find attached a basic model using the block. https://www.mathworks.com/help/hdlcoder/ref/sinehdloptimizedandcosinehdlopt...
4 mois il y a | 0
Regarding HDL_Coder license
Please reach out to the tech support and connect with the licensing team.
5 mois il y a | 0
HDL Coder generated Verilog code for 2-D LUT block propogates X in Vivado Simulator
Could you please share the sample model? The input types and block parameters are essential for generating HDL code. Addition...
5 mois il y a | 0
Error in Setup for HDL Coder Support Package for AMD FPGA and SoC Devices
What version of MATLAB are you using? Have you reached out to tech support?
5 mois il y a | 0
Why am I getting the error "found unsupported dynamic matrix type" in HDL Coder R2024b?
Related Thread https://www.mathworks.com/matlabcentral/answers/2179433-why-does-hdl-code-generation-give-errors-when-variable-s...
5 mois il y a | 0
Discrepancy between Simulink and hdl code behaviour
Could you reach out to tech support for assistance, or alternatively, share your model here? We’d be happy to take a look and pr...
6 mois il y a | 0
i want to implement 5G NR OFDM system in verilog code using HDL coder
https://www.mathworks.com/help/soc/ug/5g-nr-intro-downlink-signal-detection-rfsoc.html This example shows how to deploy a 5G ...
7 mois il y a | 0
