Part 1: Vision Processing FPGA and ASIC Hardware Considerations Learn about some of the key factors to consider when targeting a vision processing algorithm to FPGA or ASIC hardware.

Part 2: Workflow from a Frame-Based Algorithm to a Pixel-Streaming Implementation Reuse MATLAB vision processing scripts and algorithms to verify a Simulink hardware implementation.

Part 3: Hardware Design of a Lane Detection Algorithm Learn about the hardware implementation techniques used in the Vision HDL Toolbox lane detection example.

Part 4: Targeting a Lane Detection Design to a Xilinx Zynq Device Generate optimized fixed-point HDL to target the lane detection example to FPGA fabric.

Part 5: Hardware-Software Prototyping of a Lane Detection Design Prototype a hardware-software implementation of an automated driving application using the Computer Vision Toolbox Support Package for Xilinx Zynq-Based Hardware.