Génération de code HDL pour FPGA
Une simulation sur FPGA peut être judicieuse pour les modèles ou sous-systèmes exigeant des temps d’échantillonnage très courts. Si vous disposez de HDL Coder™, vous pouvez convertir votre modèle de système physique Simscape en modèle d’implémentation HDL que vous pouvez ensuite utiliser pour générer du code HDL à déployer sur un FPGA. Pour déployer un modèle ou sous-système Simscape sur un FPGA :
Utilisez la fonction
sschdladvisorpour lancer Simscape HDL Workflow Advisor qui vous guidera tout au long du processus de création du modèle d’implémentation HDL.Convertissez le modèle d’implémentation en code HDL avec l’outil HDL Workflow Advisor.
Utilisez Simulink® Real-Time™ pour déployer le code HDL sur un FPGA.
Vous pouvez utiliser la synthèse du modèle pour prédire le pas de temps réalisable sur le hardware.
Fonctions
sschdladvisor | Open Simscape HDL Workflow Advisor |
simscape.findNonlinearBlocks | Check model for blocks with nonlinear equations |
sschdl.updateRuntimeParameters | Generate updated tunable parameter data file for Simscape model (depuis R2024a) |
sschdl.generateOptimizedModel | Replace Simscape switches and converter blocks with dynamic switches optimized for FPGA deployment (depuis R2024a) |
Rubriques
- Get Started with Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Simscape™ Hardware-in-the-Loop workflow modeling guidelines and restrictions.
- Linearize a Simscape Model to Prepare for HDL Code Generation
Learn how to linearize a model that uses the Backward Euler solver for HDL deployment.
- Generate HDL Code for FPGA Platforms from Simscape Models
Learn how to convert Simscape models to HDL Code for FPGA Deployment.
- Generate Optimized HDL Implementation Model from Simscape (HDL Coder)
Optimize area and timing of HDL implementation model generated from Simscape by using HDL Coder optimizations.
- Generate and Validate HDL Code for Simscape Model (HDL Coder)
Generate HDL code from Simscape switched linear models.
- Generate HDL Code for Simscape Models with Multiple Networks (HDL Coder)
Split a large Simscape network into multiple networks and generate HDL implementation model.
- Generate HDL Code for Simscape Three-Phase PMSM Drive Containing Averaged Switch (HDL Coder)
Generate HDL code and synthesize the results for a three-phase PMSM Simscape models with converter blocks that have averaged switches and deploy onto the FPGAs.
- Simulate Large Time Steps Using Trapezoidal Rule Solver for Real-Time FPGA Deployment (HDL Coder)
Generate HDL code for a Simscape model by using the Trapezoidal Rule solver and deploy it onto a Speedgoat® FPGA I/O module.
- Generate HDL Code for Simscape Models by Using Dynamic Switch Approximation (HDL Coder)
Generate HDL code and synthesize the results for a three-phase PMSM drive using Dynamic Switch Approximation method.
- Improve FPGA Sampling Frequency of HDL Implementation Model Generated from Simscape Algorithm (HDL Coder)
Oversampling in generated HDL implementation model, and relation between model sample time and sample time of original Simscape algorithm.
- Validate HDL Implementation Model to Simscape Algorithm (HDL Coder)
Validate and resolve simulation mismatch between Simscape algorithm and HDL implementation model.
- Synthesis Results for Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Access synthesis results for Simscape hardware-in-the-loop workflow example models.
Résolution des problèmes
Resolving Issues with Nonlinearities
Troubleshoot simulation and code generation issues associated with nonlinearities.
Troubleshooting Real-Time Hardware Deployment Issues in Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Troubleshoot real-time hardware deployment issues in Simscape Hardware-in-the-Loop workflow.
Troubleshoot Validation Errors in Simscape Hardware-in-the-Loop Workflow (HDL Coder)
Troubleshoot validation mismatches in Simscape Hardware-in-the-Loop workflow.
Sélection d՚exemples
Generate Optimized Simscape Three-Phase PMSM Drive Model for Real-Time FPGA HIL Deployment
Optimize three-phase PMSM model from a Simscape model for HDL code generation and FPGA deployment.
Generate HDL Code for Two-Speed Transmission Model Containing Mode Charts
Generate HDL code and synthesize the results for a two-speed transmission model with braking that contains mode charts.
Pont redresseur double alternance
Cet exemple montre comment dimensionner un condensateur pour une charge spécifique dans un transformateur qui convertit 120 VAC en 12 VDC. Le système est modélisé comme un transformateur AC idéal associé à un pont redresseur double alternance.
